The present invention relates generally to circuitry for memory cell arrays, such as circuitry that may be used for voltage regulators for erasable, programmable read only memories (EPROMs), electrically erasable, programmable read only memories (EEPROMs), and flash EEPROM memories, for example.
Voltage regulators are circuits useful for providing accurate analog voltages for erasable, programmable read only memories (EPROMs) and other integrated circuits. A voltage regulator may typically comprise a reference voltage, a comparator, a driver and a resistor divider. An example of a prior art voltage regulator is shown in FIG. 1, and uses a so-called Miller architecture, well known in the art. A comparator GM1 is connected to the gate of a PMOS (p-channel metal oxide semiconductor) driver GM2. The comparator GM1 is supplied a supply voltage VPP, and compares voltages IP and FB. The comparator GMI adjusts the gate voltage of the PMOS driver GM2 to equalize voltages IP and FB. The output voltage, OP, is thus a multiple of the input voltage, IP. The multiplication factor is determined by the resistor divider (RD) ratio between OP and FB.
A problem with this type of regulator is that a large current (typically  greater than 100 xcexcA) is required across the resistor divider RD in order to establish the multiplication factor. It is possible to make this current arbitrarily small by increasing the resistance of the divider. However, this may have several undesirable effects. First, the drive capability of the regulator may be lowered. Second, increasing the resistance may require significant silicon area. Third, the speed of the feedback is a function of the current, and as such, lowering the current may substantially degrade the regulator""s stability.
In EPROM applications, the VPP supply (FIG. 1) is usually a pumped voltage. Pumping from the chip supply (VDD) to a higher voltage (VPP) is a process that has a low efficiency. Any current consumption from VPP requires a significantly larger current consumption from VDD, usually by a factor of 5-10. As such, it is critical to conserve current in regulators operating from a boosted source, such as those providing the wordline voltage in EPROMs. In the regulator of FIG. 1, the resistor divider drains current from the VPP supply, such that a current of 100 xcexcA required across the resistor divider may mean a VDD current of 1 mA.
Accordingly, there is a need for a regulator that has a low current consumption from VPP or another supply, while providing a high drive capability.
The present invention seeks to provide a stack element circuit that may be used to provide an improved voltage regulator. The present invention may comprise stacked diode-connected transistors that receive a reference current or a multiple thereof from a reference element, which may be a reference transistor. Diode-connected transistors are transistors whose gate is connected to the drain. The diode-connected transistors and the reference element are preferably matched such that a gate-source voltage of the diode-connected transistors is generally the same as the gate-source voltage of the reference element.
There is thus provided in accordance with a preferred embodiment of the present invention a circuit including a reference element adapted to provide a reference current and having a control terminal and a first terminal, there being a voltage (Vct) between the control terminal and the first terminal of the reference element, and a plurality of series-connected stack elements, each the stack element including a first terminal connected to a first voltage, and a control terminal connected to a second terminal, the stack elements being adapted to receive at least one of the reference current and a multiple of the reference current, the stack elements and the reference element being matched such that a voltage between the control terminal and the first terminal of at least one of the stack elements is generally the same as Vct.
In accordance with a preferred embodiment of the present invention a voltage between the control terminal and the first terminal of each the stack element is generally the same as Vct.
Further in accordance with a preferred embodiment of the present invention one of the first and second terminals comprises an input and the other of the first and second terminals comprises an output, and the output of a first stack element is connected to the input of a subsequent stack element.
Still further in accordance with a preferred embodiment of the present invention the reference element is at a voltage VDD and the stack elements are at voltage VPP wherein VPPxe2x89xa7VDD.
In accordance with a preferred embodiment of the present invention the stack elements include diode-connected transistors and the reference element includes a transistor, the diode-connected transistors and the reference element being matched such that a gate-source voltage of the diode-connected transistors is generally the same as Vct.
Further in accordance with a preferred embodiment of the present invention the reference element is adapted to have a fixed Vct voltage.
Still further in accordance with a preferred embodiment of the present invention the circuit includes a voltage regulator having an input and an output, wherein the input is a control terminal of the reference element, and the output is an output of a top transistor of the stack, the top transistor being the first of the diode-connected transistors that receives the reference current.
In accordance with a preferred embodiment of the present invention the first terminal includes an input and the second terminal includes an output.
In accordance with a preferred embodiment of the present invention the stack elements and the reference element include NMOS (n-channel metal oxide semiconductor) transistors, and the first terminal includes an input including at least one of a source and bulk, the control terminal includes a gate, and the second terminal includes an output including a drain.
Further in accordance with a preferred embodiment of the present invention the reference element receives a reference voltage at the control terminal and the output generates the reference current.
Still further in accordance with a preferred embodiment of the present invention the stack elements and the reference element include NMOS transistors, wherein for each NMOS transistor, a resistor is connected between a source of the transistor and the first terminal, a bulk of the transistor is connected to at least one of the source and the first terminal, the control terminal includes a gate, the first terminal comprises an input of the stack element and the second terminal includes an output including a drain.
Additionally in accordance with a preferred embodiment of the present invention an input of the reference element is at ground (GND).
In accordance with a preferred embodiment of the present invention an output of the circuit is the output of the top stack element, the top stack element being the first of the stack elements that receives the reference current.
Further in accordance with a preferred embodiment of the present invention a bottom stack element, the bottom stack element being the last of the stack elements that receives the reference current, receives a second reference voltage at its input.
Still further in accordance with a preferred embodiment of the present invention the stack elements and the reference element include NMOS transistors, and the first terminal includes an input including at least one of a source and bulk, the control terminal includes a gate, and the second terminal includes an output including a drain, wherein the reference element receives a reference voltage at the control terminal and the output generates the reference current, wherein an input of the reference element is at ground (GND), wherein an output of the circuit is the output of the top stack element, the top stack element being the first of the stack elements that receives the reference current, and wherein a bottom stack element, the bottom stack element being the last of the stack elements that receives the reference current, receives a second reference voltage at its input.
In accordance with another preferred embodiment of the present invention the first terminal includes an output and the second terminal includes an inputs Further in accordance with a preferred embodiment of the present invention the stack elements and the reference element include PMOS (p-channel metal oxide semiconductor) transistors, and the first terminal includes an output including at least one of a source and bulk, the control terminal includes a gate, and the second terminal includes an input including a drain.
Still further in accordance with a preferred embodiment of the present invention the stack elements and the reference element include PMOS transistors, wherein for each PMOS transistor, a resistor is connected between a source of the transistor and the first terminal, a bulk of the transistor is connected to at least one of the source and the first terminal, the control terminal includes a gate, the first terminal comprises an input of the stack element and the second terminal includes an input including a drain.
Additionally in accordance with a preferred embodiment of the present invention the control terminal and the input of the reference element are at GND.
In accordance with a preferred embodiment of the present invention a reference voltage is placed at the output of the reference element.
Further in accordance with a preferred embodiment of the present invention the control terminal of a bottom stack element the bottom stack element being the last of the stack elements that receives the reference current, receives a second reference voltage and the input of the bottom stack element is at GND.
Still further in accordance with a preferred embodiment of the present invention the stack elements and the reference element include PMOS transistors, and the first terminal includes an output including at least one of a source and bulk, the control terminal includes a gate, and the second terminal includes an input including a drain, wherein the control terminal and the input of the reference element are at GND, wherein a reference voltage is placed at the output of the reference element, wherein an output of the circuit is the output of the top stack element, the top stack element being the first of the stack elements that receives the reference current, and wherein the control terminal of a bottom stack element, the bottom stack element being the last of the stack elements that receives the reference current, receives a second reference voltage and the input of the bottom stack element is at GND.
In accordance with a preferred embodiment of the present invention the reference element is connected to the stack elements via a current mirror.
Further in accordance with a preferred embodiment of the present invention the current mirror includes at least two matched transistors.
Still further in accordance with a preferred embodiment of the present invention a voltage across the stack elements includes the Vct multiplied by a number of the stack elements.
In accordance with a preferred embodiment of the present invention a first reference voltage (VREF) is input to the reference element.
Further in accordance with a preferred embodiment of the present invention a second reference voltage is input to the stack elements.
Still further in accordance with a preferred embodiment of the present invention the second reference voltage includes the first reference voltage divided by a voltage divider.
Additionally in accordance with a preferred embodiment of the present invention the second reference voltage is equal to the first reference voltage divided by a predetermined factor Y, and wherein an output OP of the circuit is given by OP=(Sxc3x97VREF)+(VREF/Y) wherein S=the number of stack elements.
In accordance with a preferred embodiment of the present invention the voltage divider includes a resistor divider. The resistor divider may be buffered by a buffer. The output of the buffer may be input to the stack elements. The resistor divider may include a variable resistor divider or a digitally controlled resistor divider, for example.
Further in accordance with a preferred embodiment of the present invention there is a shunting path to at least one of the stack elements.
There is also provided in accordance with a preferred embodiment of the present invention a driver including fist and second PMOS transistors, first and second NMOS transistors, and first and second current sources, wherein a gate and a drain of the first PMOS transistor are connected to the first current source, and the first current source is grounded, and wherein a source of the first PMOS transistor is connected to a source of the first NMOS transistor, the first NMOS transistor having its gate and its drain connected to the second current source, the second current source being connected to a supply voltage, and wherein gates of the NMOS transistors are connected to each other, and gates of the FMOS transistors are connected to each other, and wherein a drain of the second NMOS transistor is connected to the supply voltage and a source of the second NMOS transistor is connected to an output of the driver, and wherein a drain of the second PMOS transistor is connected to GND, and a source of the second PMOS transistor is connected to the output of the driver.
In accordance with a preferred embodiment of the present invention the first and second current sources are derivable from a reference current.
Further in accordance with a preferred embodiment of the present invention the first and second current sources are generally equal.
Still further in accordance with a preferred embodiment of the present invention an input to the driver is connected to an output of a circuit including a reference element adapted to provide a reference current and having a control terminal and a first terminal, there being a voltage (Vct) between the control terminal and the first terminal of the reference element, and a plurality of series-connected stack elements, each the stack element including a fist terminal connected to a first voltage, and a control terminal connected to a second terminal, the stack elements being adapted to receive at least one of the reference current and a multiple of the reference current, the stack elements and the reference element being matched such that a voltage between the control terminal and the first terminal of at least one of the stack elements is generally the same as Vct, wherein a first reference voltage (VREF) is input to the reference element, and wherein a second reference voltage is input to the stack elements.
There is also provided in accordance with a preferred embodiment of the present invention a circuit including a reference element adapted to receive a first reference voltage and provide a reference current, and a plurality of series-connected stack elements adapted to receive the reference current and provide a multiple of the fist reference voltage, wherein the multiple is a function of the number of the stack elements.